VLSI Online for Novice by Learnyzen

Programming basics: Data types and operators
Conditional and looping constructs
Data structures
Digital Design & Verification
Linux Shell Scripting/Python
Digital fundamentals - ASIC design and verification flow - Verilog language - Verilog for design and verification, Synthesizable constructs
Combinational design
Sequential design
Synchronous and asynchronous design
Finite State Machine

Advance Digital Design/Verification - System Verilog Language - Verilog Testbench Design
Events and delays
Clock and reset generation
Tasks and functions
Testcases
Checkers and scoreboard
Test plan creation
UVM Methodology - Verification Project Flow - AMBA protocols (APB/AXI)
Introduction to UVM
UVM architecture
UVM Phases
TLM
UVC design (Driver, monitor, sequencer and agents)
Sequences and testcases
Configuration database
Callbacks
UVM testbench design

Protocols
Verification project flow
Advance design concepts
Projects in Verilog, System Verilog and UVM
VIP development
E-mail communication
Presentations
Documentation
Mock interviews