VLSI Online Beginner level by VLSI Guru Training Institute

VLSI TRAINING COURSE CONTENT :
1. VLSI Design Flow
2. SoC Architecture Concepts
3. On-Chip Bus Protocols (AXI4.0, OCP3.0)
4. Peripheral Bus Protocols(USB3.0/PCIEx Gen3)
5. Advanced Verilog for Verification
6. SystemVerilog for Advanced Verification
7. ASIC Verification Concepts
8. ASIC Verification Methodologies : OVM & UVM
9. PERL Automation
10. PROJECTS : Module(IP) Level Verification Projects
o Project#1 : SystemVerilog Based Project based Complex IP (USB, Ethernet, MemCtrl, Bridge, etc)
o Project#2 :SV & OVM/UVM Based Project based on Complex IP (UART, KBD, Bridge, etc)
11. System on Chip(SoC) Verification Concepts
12. Mock Interviews & Group Discussions
13. Student assignments for weekday practice

Detailed Course Structure :
1. VLSI Design Flow
o SoC Design Flow
o IP Design Flow
o ASIC/FPGA Flow
2. SoC Architecture Concepts
o ARM Processor Architecture
o L1/L2/L3/L4 Interconnects
o On-Chip Bus Protocols
o Bridge Protocols
o Controllers Modules
o Peripheral bus Protocols
o L1/L2 Cache, On-chip memory
o Boot sequence & Sub System Bringup
o Low Power Design Techniques
3. On-Chip Bus Protocols (AXI4.0, OCP3.0)
o Signal Descriptions
o Channel Handshake
o Addressing Options
o Atomic Accesses
o Response Signalling
o Ordering Model
o Data buses
o Unaligned Transfers
o Clock, Reset
o AXI4 Specific revision updates
4. Peripheral Bus Protocols(USB3.0/PCIEx Gen3)
o USB3.0 Architectural Overview
o Data Flow Model
o Physical Layer
o Link Layer
o Protocol Layer
5. Advanced Verilog for Verification
o Event Regions and Event Scheduling
o Tasks and Functions
o Race Conditions
o Randomization
o File I/O operations
o TB Constructs
o Self Checking Testbenches
6. SystemVerilog for Advanced Verification
o Arrays
o Data Types and Data Declarations
o Classes
o Operators and Expressions
o Scheduling Semantics
o Procedural Statements and control flow
o Processes & Threads
o Tasks and Functions
o Random Constraints
o Inter Process synchronization and communication
o Clocking blocks, Program Block, Assertions
o Coverage, Interface
o System Tasks and System Functions
o Compiler Directives
o DPI
7. ASIC Verification Concepts
o SoC Verification
o Module Level Verification
o Constrained Random Verification
o Coverage Driven Verification
o Directed Verification
o Assertion Based Verification
8. ASIC Verification Methodologies : OVM & UVM
o OVM/UVM TB Architecture
o Stimulus Modeling
o Creating OVCs and Environment
o OVM Simulation Phases
o TLM Overview
o Configuring TB Environment
o OVM Sequences and Sequencers
o Connecting multiple OVCs
o Creating TB infrastructure
o Advanced OVM/UVM Concepts
9. PERL Automation
o Data types and Objects
o Regular Expressions & Subroutines
o Regression environment setup
o PERL in verification environment setup
10. PROJECTS : Module(IP) Level Verification Projects
o Project#1 : SystemVerilog Based Project
o Project#2 :SystemVerilog & OVM/UVM Based Project
Project designs : Complex module (USB/Ethernet/KBD/MemContrlr/Bridge protocols etc)
Specification analysis
Verification Plan creation
Feature & Scenario Listing down
TB architecture creation
Building Top level verification environment
TB component coding and integration
Sanity test case and environment bring up
Complete test case coding
Building regression test suite
Functional coverage and code coverage analysis
11. System on Chip(SoC) Verification Concepts
o Project Category : Medium complex SoC
o TB Architecture creation
o Building top level verification environment
o TB component coding and integration
o Sanity test case and environment bring up
o Complete test case coding
Functional, Timing, Power &Performance Tests
Reset Value, Register access, Interrupt, Power Related, Functional Tests
o Building regression test suite
12. Mock Interviews & Group Discussions (Session# 16 & 28)
o Mock Interviews covering all aspects of Functional Verification
o Group discussion on Project assigned to students
13. Assignments provided to student during course
o VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
o Verification of PCIEx Physical Layer LTSSM FSM from scrach
o Functional Verifcation of UART/AXI-DMA/OCP2AXI Bridge from scratch