VLSI course Beginner level by NXFee Inovation

VLSI COURSE SYLLABUS

SECTION - 1
Sno. INTRODUCTION
1. Introduction to VLSI
2. Introduction to HDL languages
3. Introductioin to Verification methodology
4. Introduction to Design flow and modeling

SECTION - 2
Sno. INTRODUCTION TO VHDL
1. Introduction to Language Basic
2. What is VHDL
3. VHDL objects
4. VHDL connection model
5. Hierarchy
6. Rules and Regulation
7. Stimulus from VHDL

SECTION - 3
Sno. SIGNALS AND DATA TYPES
1. TYPE CONCEPT
2. STANDARD DATA TYPE
3. SIGNAL AND DRIVERS
4. ARRAYS DECLARATION/ ARRAYS ASSIGNMENTS
5. BIT STRING LITERAL
6. CONCATENATION
7. SLICE OF AN ARRAY
8. AGGREGATES
9. TYPE DEFINITIONS
10. STANDARD LOGIC

SECTION - 4
Sno. VHDL OPERATORS/CONCURRENT AND SEQUENTIAL STATEMENTS
1. LOGICAL OPERATORS
2. RELATIONAL OPERATORS
3. ARITHMETIC OPERATORS
4. CONCURRENT SIGNAL ASSIGNMENTS
5. PROCESS DECLARATION
6. SEQUENTIAL STATEMENTS
SECTION - 5
Sno. VHDL OPERATORS/CONCURRENT AND SEQUENTIAL STATEMENTS
1. LOGICAL OPERATORS
2. RELATIONAL OPERATORS
3. ARITHMETIC OPERATORS
4. CONCURRENT SIGNAL ASSIGNMENTS
5. PROCESS DECLARATION
6. SEQUENTIAL STATEMENTS
7. CONCURRENT VS SEQUENTIAL
8. MULTIPLE PROCESS CALL
9. VARIABLES
10. SIGNALS VS VARIABLES
11. SEQUENTIAL INSTRUCTIONS

SECTION - 6
Sno. SYNTHESIS
1. RTL DESCRIPTION
2. TIMING CONSTRAINTS
3. TECHNOLOGY LIBRARIES
4. TRANSLATE/MAPPING
5. PLACE AND ROUTE

SECTION - 7
Sno. SYNTHESIS ISSUES
1. SYNTHESIS ARCHITECTURE / LOGIC
2. REGISTER INFERENCE
3. WHAT IS RTL STYLE
4. DESCRIBING AN FSM
5. VECTOR ARITHMETIC

SECTION - 8
Sno. ADVANCE VHDL
1. MORE FLEXIBLE CODE
2. SUBPROGRAMS
3. GENERICS AND GENERATE
4. ATTRIBUTES
5. MODELING DELAY
6. PASSING DELAYS THROUTH CONFIGURATIONS
7. HANDLING UNKNOWNS

SECTION - 9
Sno. BEHAVIORAL SIMULATION
1. BASIC TEST BENCHS
2. WORKSHOP IN MODELSIM

SECTION - 10
Sno. RTL SIMULATION
1. BASIC TEST BENCHS
2. WORKSHOP IN XILINX
3. WORKSHOP IN COREGENARATOR

SECTION 11
Sno. BOARD LEVEL TESTING
1. FPGA INTRODUCTION
2. BOARD LEVEL TESTING

SECTION 12
Sno. MINI PROJECT
1. CONCEPT
2. UNDERSTANDING DOCUMENT
3. RTL LEVEL DESIGN
4. SIMULATION VS HARDWARE